1. Field of the Invention
The present invention relates to a slurry composition, a polishing method using the slurry composition, and a method of forming a gate pattern using the slurry composition. More particularly, the present invention relates to a slurry composition for polishing a polysilicon layer in a chemical mechanical polishing process, a polishing method using the slurry composition, and a method of forming a gate pattern using the slurry composition.
2. Description of the Related Art
A multi-layer wiring structure is typically employed in a semiconductor device, as the semiconductor device is required to have high capacity and a high degree of integration. The multi-layer wiring structure is generally formed through repeatedly performing processes for forming a conductive layer, and an insulation layer and through repeatedly performing etching processes for patterning the conductive layer and the insulation layer. After the conductive layer and the insulation layer are etched to form a conductive layer pattern and an insulation layer pattern, planarization processes are carried out about the conductive layer pattern and the insulation layer pattern. Successive photolithography processes for forming the conductive layer pattern and the insulation layer pattern may be more efficiently performed when the patterns are so planarized.
Planarization processes are typically divided into a local planarization process or a global planarization process. Etch-back, reflow and chemical mechanical polishing processes are typical planarization processes.
The chemical mechanical polishing (CMP) process is usually employed for forming integrated circuits having a high degree of integration, because the chemical mechanical polishing process efficiently performs global planarization of the polished layers. The chemical mechanical polishing process, as developed by International Business Machines (IBM) Corp., typically involves a semiconductor substrate disposed beneath a polishing head of a chemical mechanical polishing and a polishing pad positioned under the semiconductor substrate. A slurry composition, including deionized water, an abrasive and an additive, is provided onto the semiconductor substrate. The semiconductor substrate and the polishing pad may be moved with respect to each other while the polishing pad makes contact with the semiconductor substrate so that a surface portion of the semiconductor substrate is planarized. The abrasive of the slurry composition and protrusions of the polishing pad may mechanically polish the surface portion of the semiconductor substrate. Simultaneously, the surface portion of the semiconductor substrate is chemically polished by reactions between chemical components included in the slurry composition and ingredients in the surface portion of the semiconductor substrate.
A polishing efficiency of the chemical mechanical polishing process may be determined by multiple factors, including the nature of the chemical mechanical polishing apparatus, the make-up of the slurry composition, and type of the polishing pad. Typically, the polishing efficiency is mainly determined by the slurry composition.
In forming a gate pattern of a semiconductor device, a polysilicon layer is typically formed on a silicon oxide layer pattern, the silicon oxide layer serving as a polishing stop layer. Then, the polysilicon layer is polished.
A processing time of the chemical mechanical polishing process on the polysilicon layer may be lengthened, however, if a slurry composition having a low removal rate of the polysilicon layer is used in the chemical mechanical polishing process. In addition, when the silicon oxide layer pattern is exposed by removal of a portion of the polysilicon layer, which is positioned on the silicon oxide layer, erosion or dishing of the polysilicon layer may occur at a surface portion of the polysilicon layer and/or a surface portion of a semiconductor substrate.
FIG. 1 illustrates a cross-sectional view of a wafer, showing erosion and dishing of the polysilicon layer. FIG. 2 illustrates an enlarged cross-sectional view of a wafer, showing a portion “A” of FIG. 1.
Referring to FIGS. 1 and 2, recesses may be formed across a whole surface portion of a polysilicon layer 102 during a chemical mechanical polishing process. The recesses generated across the whole surface portion of the polysilicon layer 102 are defined as erosion of the polysilicon layer 102. As illustrated in FIG. 2, recesses may also be formed locally at portions of the polysilicon layer 102. Such recesses are defined as dishing of the polysilicon layer 102.
When a polishing selectivity between the polysilicon layer 102 and a polishing stop layer pattern 101 is low, erosion of the polysilicon layer 102 may easily occur. In addition, when the polishing selectivity is low, polishing of the polishing stop layer pattern 101 may readily occur, concurrently with polishing of the polysilicon layer 102. That is, the polishing stop layer pattern 101 may not precisely stop polishing of the polysilicon layer 102, so that erosion of the polysilicon layer 102 may occur. Furthermore, erosion of the polysilicon layer 102 may increase a height difference between a maximum height (h1) and a minimum height (h2) in the polysilicon layer 102. As a result, polishing uniformity of the polysilicon layer 102 may decrease.
In contrast, when the polishing selectivity is high, chemical components included in the slurry composition chemically polish the polysilicon layer 102, while the polishing stop layer pattern 101 may prevent mechanical polishing of the polysilicon layer 102 by the polishing pad. As a result of this imbalance between the chemical and mechanical aspects of the chemical mechanical polish, dishing of the polysilicon layer 102 may occur, as illustrated in FIG. 2.